1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device provided with transistors having a plurality of gate insulating films with different film thicknesses.
2. Description of the Related Art
Semiconductor devices such as flash memories comprise a memory cell region in which a number of memory cell transistors are formed and a peripheral circuit region including high breakdown voltage transistors. The high breakdown voltage transistors are formed with gate oxide films with film thicknesses differing from each other according to different gate breakdown voltages respectively. The transistors are isolated from each other by shallow trench isolation (STI). The above-described configuration is dominant. Furthermore, a self-aligned contact structure is employed for improvement in high integration in a process of forming contact holes.
One type of semiconductor device has a structure that oxide films are formed on sidewalls of gate electrodes for improvement in the reliability of the gate electrodes. A silicon nitride film is used as a stopper when contact holes are formed by self-aligned contact in this type of semiconductor device. In this case, however, an inconvenience occurs in relation to the use of silicon nitride film as the stopper. In view of the inconvenience, the prior art has employed a method as disclosed in JP-A-2002-57230. In the disclosed method, an oxide film in the contact hole forming region is previously removed and then, a silicon nitride film is formed.
On the other hand, in the configuration employing the aforesaid self-aligned contact, another problem arises which results from a difference in height between an STI structure as an element isolation insulating film and a silicon substrate. More specifically, when a silicon oxide film and a silicon nitride film are formed after formation of a gate electrode, the silicon nitride film remains in a stepped portion of the STI structure as if the film served as a spacer. Accordingly, a contact area of the gate electrode with the silicon substrate is reduced, which results in an increase in the contact resistance. In order that this inconvenience may be overcome, an etchback process is carried out for the silicon oxide film buried in a groove of the STI structure before formation of the silicon nitride film serving as a stopper, so that the difference in height is reduced between the surface of the silicon substrate and the STI structure.
However, when the above-described fabrication process is executed, a surface layer of the silicon substrate in a region around the gate electrode is etched. The etched surface layer of the silicon substrate is a factor reducing a short channel characteristic as an operating characteristic of the memory cell. As a countermeasure, for example, before a thick gate oxide film and STI are etched so as to reach the level of the silicon substrate surface, a portion where a thin gate oxide film is formed, such as a memory cell transistor or low breakdown voltage transistors, are suggested to be masked by a photoresist or the like so that the silicon substrate is prevented from being etched. However, since this method necessitates a photolithography to be added, the number of steps in the fabrication process is increased and accordingly, the costs are increased. Thus, a fabrication method that does not necessitate addition of the photolithography process has been desired.